A fractional divider system and method

摘要

The present invention relates to a fractional divider system (100) for low-power timer with reduced timing error at wakeup. The fractional divider system (100) comprises a fractional divider means (102) operable to produce an output signal with a frequency F C with the following relation to a reference clock frequency F LP : F LP = ( M + N P DIV ) × F c , wherein P DIV is the period of said fractional divider means (102), M is the integer part of the division ratio, and N is the magnitude of the fractional part of the division ratio. The fractional divider system (100) also comprises a to said fractional divider means (102) connected high speed crystal oscillator means (104) operable to start on wakeup from the low power mode. The fractional divider system (100) also comprises a to said high speed crystal oscillator means (104) connected high speed clock divider means (106). The high speed crystal oscillator means (104) also is operable to sample the output signal and a current state of the total timing error from said fractional divider means (102). The sampled output signal trigger said high speed clock divider means (106) and said sampled current state of the total timing error preloads said high speed clock divider means (106), which is operable to synchronise the first pulse of the output clock signal to the ideal clock timing to an accuracy within 1,5 periods of the high speed clock.