发明名称 Message-passing decoding of low-density parity-check (LDPC) codes using pipeline node processing
摘要 <p>In an LDPC-code decoder, bit-processing units (10-1 to 10-M) are provided, respectively, for the 1 st to M th rows of the parity-check matrix (H) that is formed of (r × s) permuted matrices having respective arrays of (m × m). Each of bit-processing units (10-1 to 10-M) sequentially updates bit information corresponding to column positions included in the respective rows of the parity-check matrix, a bit at each of the column positions being set to "1". Parity-processing units (20-1 to 20-m) update parity information corresponding to row positions in columns of each column block of the parity-check matrix, whenever the bit-processing units (10-1 to 10-M) have finished bit update computation for m column positions in each column block, a bit at each row position being set to "1". The bit-processing units (10-1 to 10-M) starts next bit update computation after the parity-processing units (20-1 to 20-m) finish parity update computation for m columns of the first column block of the parity-check matrix.</p>
申请公布号 EP1612948(A1) 申请公布日期 2006.01.04
申请号 EP20050105370 申请日期 2005.06.17
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 YOSHIDA, KENJI
分类号 H03M13/11 主分类号 H03M13/11
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