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发明名称
配线电路基板及其制造方法
摘要
本发明系提供一种配线电路基板及该配线电路基板之制造方法,系以微细间距(fine pitch)形成配线电路图案,而在该配线电路图案上,即使藉由无电解镀锡法形成镀锡层,亦可防止配线剥离者,因此,在绝缘层1之上,形成由铬之含有率为8至20重量%之镍-铬合金所成之金属薄膜2,且在金属薄膜2之上,形成由铜所成之配线电路图案4。然后,在露出配线电路图案4之表面,藉由无电解镀锡法形成镀锡层5。
申请公布号
TW200601920
申请公布日期
2006.01.01
申请号
TW094111613
申请日期
2005.04.13
申请人
日东电工股份有限公司
发明人
恒川诚;中村圭;豊泽圭子;大和岳史;马场俊和
分类号
H05K3/38
主分类号
H05K3/38
代理机构
代理人
洪武雄;陈昭诚
主权项
地址
日本
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