| 摘要 |
A ferroelectric memory device is characterized in having a first n-type MOS transistor having a gate connected to a word line, a ferroelectric capacitor having one end connected through the first n-type MOS transistor to a bit line, and another end connected to a plate line, and a plate line control circuit that drives the plate line, wherein the plate line control circuit includes an inverter having a first p-type MOS transistor and a second n-type MOS transistor, and an output terminal connected to the plate line, a voltage source that supplies a voltage to be supplied to a source of the first p-type MOS transistor, and a third n-type MOS transistor provided between the voltage source and the output terminal.
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