| 摘要 |
Diversity receiver 100 provided with receiving LSI device 10 , antennas 11 and 12 , RF circuits 25 and 26 and main CPU 27 is disclosed. Receiving LSI device 10 receives diversity signals through antennas 11 and 12 and RF circuits 25 and 26 . One of ADCs 30 and 31 and a part of CDM 32 provided in demodulator 14 are only energized to save electric power consumption when a receiving quality of the diversity signals is acceptable, or both ADCs 30 and 31 and CDM 32 are otherwise fully energized. Bit-interleave circuit 15 , Viterbi decoder 17 and receiving-quality-judgment circuit 19 connected in parallel with Viterbi decoder 17 are provided to detect an error rate for the receiving quality judgment. Further, byte-interleave circuit 20 , Reed-Solomon decoder 22 and receiving-quality-judgment circuit 24 connected in parallel with Reed-Solomon decoder 22 are also provided to detect another error rate for the receiving quality judgment. Main CPU 27 is connected to receiving LSI device 10 to supply demodulator 14 with a control signal based on the error rates detected by receiving quality judgment circuits 19 and 24.
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