发明名称 Fast bistable circuit protected against random events
摘要 A bistable circuit includes a first inverter and a capacitive inversion circuit having one input coupled to an output of the first inverter. The capacitive inversion circuit includes a second inverter and a capacitive circuit parallel-coupled to the input and an output of the capacitive inversion circuit. The bistable circuit also includes a switch to isolate the output of the capacitive inversion circuit from an input of the first inverter when the switch receives an active validation signal or, if not, to couple the output of the capacitive inversion circuit to the input of the first inverter.
申请公布号 US2005285650(A1) 申请公布日期 2005.12.29
申请号 US20050159818 申请日期 2005.06.23
申请人 CLERC SYLVAIN;ROCHE PHILIPPE;JACQUET FRANCOIS 发明人 CLERC SYLVAIN;ROCHE PHILIPPE;JACQUET FRANCOIS
分类号 G11C11/412;H03K3/037;H03K3/356;H03K19/094;(IPC1-7):H03K3/037 主分类号 G11C11/412
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