发明名称 |
Memory control apparatus and method for scheduling commands |
摘要 |
Provided are a memory control apparatus and method for controlling an order of processing memory access commands from a plurality of master devices when the master devices access a memory to improve a processing speed. The memory controller includes a command queue receiving memory access commands from at least one master device and storing the memory access commands; a determination unit analyzing addresses of a memory, which will be accessed by the received commands, to control an order of processing the stored commands; and a command interpreter interpreting a command output under the control of the determination unit to output an address related signal. Accordingly, a command processing speed is remarkably improved without increasing a system size.
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申请公布号 |
US2005289319(A1) |
申请公布日期 |
2005.12.29 |
申请号 |
US20050088793 |
申请日期 |
2005.03.25 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KANG SHIN-WOOK |
分类号 |
G06F12/00;G06F12/02;G06F13/18;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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