发明名称 |
Scalable two-transistor memory devices having metal source/drain regions and methods of fabricating the same |
摘要 |
A scalable two-transistor memory (STTM) device includes a planar transistor and a vertical transistor on a semiconductor substrate. The planar transistor includes spaced apart metal silicide source/drain regions on the substrate and a floating gate electrode on the substrate between the metal silicide source/drain regions that controls a channel region of the planar transistor. The vertical transistor includes a tunnel junction structure on the floating gate electrode and a control gate electrode on a sidewall of the tunnel junction structure that controls a channel region of the vertical transistor. Related methods of forming STTM devices are also discussed.
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申请公布号 |
US2005285183(A1) |
申请公布日期 |
2005.12.29 |
申请号 |
US20050158455 |
申请日期 |
2005.06.22 |
申请人 |
BAIK SEUNG-JAE |
发明人 |
BAIK SEUNG-JAE |
分类号 |
H01L27/10;G11C16/04;H01L21/28;H01L21/336;H01L29/423;H01L29/788;(IPC1-7):H01L29/788 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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