| 摘要 |
A memory circuit requiring refresh operations, comprising: a first circuit which receives a command (CMD) in synchronization with a clock signal (CK1), and which generates a first internal command (RD, WR) internally and a second circuit which generates a second internal command, e.g. a refresh command (REF), internally in a prescribed refresh cycle. An internal circuit, according to said first internal command (RD, WR), executes corresponding control through clock-synchronous operations, and when said refresh command (REF) is issued, sequentially executes control corresponding to the refresh command (REF) and control corresponding to said first internal command (RD, WR) through clock-asynchronous operations. When a refresh timing signal is generated, the refresh operation can be interrupted among external command operations. <IMAGE>
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