| 摘要 |
<p>The present invention relates to a method for synchronizing a number of digital clocks (PCLK) to a synchronizing signal (SYNC), said method comprising the steps of generating centrally a reference clock (RCLK), synthesizing said digital clocks (PCLK) from said reference clock (RCLK) using a clock multiplying means, respectively, resetting said clock multiplying means in response to said synchronizing signal (SYNC), and masking an output signal (VCLK) of said clock multiplying means during settling time of said clock multiplying means. <IMAGE></p> |
