发明名称 |
MEMORY MANAGEMENT IN A DATA PROCESSING SYSTEM |
摘要 |
Memory management in a data processing system ( 10 ) is achieved by using one or more timing bits ( 54 ) to specify a timing parameter of a memory ( 18, 19, 34 ). To implement this in some embodiments of the present invention, a memory array ( 32, 33, 42 ) is multiple-mapped in the physical memory map ( 70 ) of processor ( 12 ) and the address bits ( 54 ) associated with the multiple-mapping are used to directly control timing parameters of the memory arrays ( 32, 33, 42 ). This allows for flexible timing specifications to be derived quickly on an access by access basis without requiring any additional control storage overhead. |
申请公布号 |
EP1609067(A1) |
申请公布日期 |
2005.12.28 |
申请号 |
EP20040708127 |
申请日期 |
2004.02.04 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
MOYER, WILLIAM, C.;MARSHALL, RAY |
分类号 |
G06F12/00;G06F12/02;G06F12/06;(IPC1-7):G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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