| 摘要 |
The present invention relates to a method for synthesizing digital clock signals for an electronic device under test (DUT) having a plurality of pins, said method comprising the steps of generating centrally a reference clock (RCLK), and distributing said reference clock (RCLK) to a number of electronic circuits, each of said electronic circuit comprising a test signal processor (20a, 20b, 20c) controlling electrically said pins of said device under test (DUT) with predetermined signal pattern, characterized by the step of synthesizing local at said test signal processor (20a, 20b, 20c) a digital clock signal (PCLK), said digital clock signal (PCLK) being individual for said pin of said device under test (DUT) electrically controlled by said test signal processor (20a, 20b, 20c). <IMAGE>
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