发明名称 VSB modulator symbol clock processing to reduce jitter/phase noise and sampling artifacts
摘要 A translator demodulates a received digital television signal so as to produce a digital data stream, a symbol clock, and a byte clock, wherein the symbol clock and the byte clock are corrupted by phase noise. The digital data stream is written into a buffer in response to the corrupted byte clock. The corrupted symbol clock is applied to a frequency/phase locked loop having a narrowband loop filter. The frequency/phase locked loop produces a regenerated symbol clock having substantially no phase noise. The digital data stream is read from the buffer in response to the regenerated symbol clock. The digital data stream read from the buffer and the regenerated symbol clock are applied to a modulator for re-broadcasting of the received digital television signal.
申请公布号 US6980255(B2) 申请公布日期 2005.12.27
申请号 US20020279319 申请日期 2002.10.24
申请人 ZENITH ELECTRONICS CORPORATION 发明人 HAUGE RAYMOND C.;JONES GARY A.;NOWACZYK PHILIP J.
分类号 H04N5/455;(IPC1-7):H04N7/00;H04L7/00 主分类号 H04N5/455
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