发明名称 DRAM memory cell and memory cell array with fast read/write access
摘要 The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The large extent of the channel region in the bit line direction means that the trench capacitor can be rapidly charged and read. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. A conductive channel can be formed within the channel region depending on the potential of the word line.
申请公布号 US6979853(B2) 申请公布日期 2005.12.27
申请号 US20030462533 申请日期 2003.06.16
申请人 INFINEON TECHNOLOGIES AG 发明人 SOMMER MICHAEL;ENDERS GERHARD
分类号 G11C7/00;H01L21/8242;H01L27/108;H01L29/76;H01L29/94;H01L31/119;(IPC1-7):H01L27/108 主分类号 G11C7/00
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