| 摘要 |
In a display data RAM, a group of memory cells for storing grayscale data for two lines are disposed within an output pad pitch L of a display driver circuit, and at least two groups of the memory cells are arranged in a direction perpendicular to the direction in which the output pads are arranged. The grayscale data for two lines is read at a time from the display data RAM. Latch circuits latch the grayscale data for four lines based on first and second clock signals. A selector circuit selectively outputs the grayscale data for consecutive three lines from among the grayscale data latched in the latch circuit. An MLS signal conversion circuit performs MLS operation in which three lines are simultaneously selected, based on the selectively output grayscale data for three lines. A signal electrode driver circuit outputs a drive voltage to the output pads based on the MLS operation results.
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