| 摘要 |
A method for fabricating a flash memory device, to decrease a cell size by forming a control gate within a minimum line width permitted in the fabrication process, and to effectively obtain the operation characteristics even in case of the decrease of the cell size, which includes the steps of forming a gate pattern layer having a minimum line width (A) by stacking a material layer for gate and a cap insulating layer on an ONO layer of a semiconductor substrate, and primarily etching the stacked layers; forming an insulating layer for planarization on an entire substrate of the semiconductor substrate, and removing the cap insulating layer, to define a select gate formation region; forming a mask pattern layer of a sidewall shape in the select gate formation region, and secondarily etching the gate pattern layer by using the mask pattern layer, to form control gates; and forming a select gate isolated from the control gates in the select gate formation region, and forming source and drain junction regions in the surface of the semiconductor substrate at both sides of the select gate.
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