发明名称 |
Low power, minimal area tap multiplier |
摘要 |
A low power tap multiplier multiplies a m-bit multiplier and a n-bit multiplicand to output a p-bit multiplication product. The p-bit product is one bit more than the n-bit multiplicand when the multiplicand is symmetric, and two bits more when the multiplicand is non-symmetric. Since the low power tap multiplier utilizes a minimal number of small unstacked transistors, it consumes less power and requires less silicon area.
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申请公布号 |
US6981013(B1) |
申请公布日期 |
2005.12.27 |
申请号 |
US20010963042 |
申请日期 |
2001.09.24 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
PASQUALINI RONALD |
分类号 |
G06F7/52;G06F7/53;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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