发明名称 |
Memory architecture with segmented writing lines |
摘要 |
A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.
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申请公布号 |
US2005281090(A1) |
申请公布日期 |
2005.12.22 |
申请号 |
US20050152033 |
申请日期 |
2005.06.14 |
申请人 |
STMICROELECTRONICS S.A. |
发明人 |
DRAY CYRILLE;BARASINSKI SEBASTIEN;LASSEUGUETTE JEAN;FREY CHRISTOPHE;FOURNEL RICHARD |
分类号 |
G11C7/18;G11C8/10;G11C11/16;(IPC1-7):G11C16/04 |
主分类号 |
G11C7/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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