| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor device and the layout designing method thereof whereby in the layout design of the semiconductor device for disposing dummy gates in order to improving the variations of the shapes of the gate electrodes of its transistors, its layout area and its designing manhours are cut down. SOLUTION: The layout designing method comprises a process for disposing transistors, a dummy-gate producing process wherein the dummy gates whose shapes are identical with the gate electrodes of a transistor inclusive of the protruded portions from the active region of the transistor are so produced that they are made parallel with the gate electrodes, and are separated by fixed spaces from the gate electrodes disposed at both the ends of its active region which are present in the gate-length direction, and when the transistor has a plurality of gate electrodes having different gate-widths from each other, only necessary protruded portions are extended to the outside of its active region; a gate connecting process wherein, when a gate pattern and a contact region are connected with the gate electrode of the transistor dependently on their positional relations to the dummy gates, the gate electrodes and the dummy gates are connected with each other; and a wiring process wherein the wirings of metal layers are performed. By these processes, a semiconductor device having an occupied area smaller than conventional ones can be designed with designing manhours less than conventional ones. COPYRIGHT: (C)2006,JPO&NCIPI
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