| 摘要 |
When a simulation model generation unit converts logic on the gate level into a basic primitive which can be executed by a simulator to generate a simulation model, for the basic primitives a degeneracy processing unit determines and deletes a gate which can be deleted and which will not affect the delay stage count. The degeneracy processing unit is provided with a constant gate degeneracy unit which puts a plurality of constant gates together, a buffer degeneracy unit which deletes fan-out-free buffers and an identical fan-in gate degeneracy unit which puts identical fan-in gates together.
|
