发明名称 |
Test mode decoder in a flash memory |
摘要 |
Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.
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申请公布号 |
US2005280072(A1) |
申请公布日期 |
2005.12.22 |
申请号 |
US20050216263 |
申请日期 |
2005.08.31 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
NASO GIOVANNI;D'AMBROSIO ELIO |
分类号 |
G11C29/14;G11C29/46;H01L21/336;H01L21/4763;H01L21/8247;H01L27/02;H01L27/105;H01L29/76;(IPC1-7):H01L21/336;H01L21/476 |
主分类号 |
G11C29/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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