| 摘要 |
An arranging unit arranges a cell obtained from a net list input by an input unit on a large scale integration chip. A net extracting unit extracts an arbitrary net to be tested from a set of the cells arranged. An information extracting unit extracts, based on correlation information between information on a driving capacity of each of cells included in a circuit created based on a delay time caused by a crosstalk occurred as a result of a circuit simulation for a predetermined circuit model and information on a length of a wiring that connects the cells, wire-length information that has a correlation with information on the driving capacity of the cell in the net. An inserting unit inserts, based on the wire-length information, a delay-time suppressing cell to suppress a delay time in the net.
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