发明名称 Method and apparatus for reducing false error detection in a microprocessor
摘要 A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.
申请公布号 US2005283716(A1) 申请公布日期 2005.12.22
申请号 US20040871430 申请日期 2004.06.17
申请人 MUKHERJEE SHUBHENDU S;EMER JOEL S;REINHARDT STEVEN K;WEAVER CHRISTOPHER T;SMITH MICHAEL J 发明人 MUKHERJEE SHUBHENDU S.;EMER JOEL S.;REINHARDT STEVEN K.;WEAVER CHRISTOPHER T.;SMITH MICHAEL J.
分类号 G06F9/38;G06F11/10;G06F11/14;(IPC1-7):G06F11/00;H03M13/00;G11C29/00 主分类号 G06F9/38
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