发明名称 LSI DESIGN METHOD
摘要 PROBLEM TO BE SOLVED: To shorten the period for LSI development by shortening the time required for verifying a timing condition of LSI. SOLUTION: In an initial stage of design, an undetermined quantity of timing caused by indetermination of the influence on timing of each item associated with setting of a time margin is estimated in conformation to each item. In each stage of design, the timing margin is set by use of the estimation result in conformation to whether the influence of each item is determined or not to perform the design of each stage. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005352916(A) 申请公布日期 2005.12.22
申请号 JP20040174722 申请日期 2004.06.11
申请人 FUJITSU LTD 发明人 HOSONO TOSHIKATSU;YONEDA TAKASHI
分类号 G06F17/50;H01L21/82;H03K19/00;H03K19/0175;(IPC1-7):G06F17/50;H03K19/017 主分类号 G06F17/50
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