HIGH PERFORMANCE CMOS TRANSISITORS USING PMD LINEAR STRESS
摘要
A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The asformed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.
申请公布号
WO2005106940(A3)
申请公布日期
2005.12.22
申请号
WO2005US13872
申请日期
2005.04.22
申请人
TEXAS INSTRUMENTS INCORPORATED;BU, HAOWEN;KHAMANKAR, RAJESH;GRIDER, DOUGLAS, T.