发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL CIRCUIT |
摘要 |
Problems are prevented that a refresh provides an influence to a normal access and that a continuation of write operations inhibits refresh. <??>In a semiconductor memory device, a clock signal providing a reference to a time interval of refresh operations based on addresses corresponding to a single row is generated as a refresh clock signal. A transition of an access address "Address" externally supplied and corresponding to a memory cell is detected, so that a refresh operation is executed to a memory cell corresponding to a refresh address by triggering the generation of this detection signal before an access to a memory cell designated by the access address is made, wherein upon the input of a write enable signal /WE, the refresh is executed by triggering this signal before a write operation is executed and the refresh operation by triggering the generation of the access address is discontinued in a predetermined period of time based on the refresh clock signal. <IMAGE> |
申请公布号 |
EP1351250(A4) |
申请公布日期 |
2005.12.21 |
申请号 |
EP20010270215 |
申请日期 |
2001.12.06 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
TAKAHASHI, HIROYUKI;KUSAKARI, TAKASHI |
分类号 |
G11C11/403;G11C11/406 |
主分类号 |
G11C11/403 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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