发明名称 |
Timing synchronization methods and systems for transmit parallel interfaces |
摘要 |
Transmit parallel interfaces and methods are provided in which a clock signal is generated that maximizes the setup and hold window of input data. In at least some embodiments, a divider circuit provides a clock signal in one clock domain that has a rising edge located very close to the falling edge of a system clock in another clock domain.
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申请公布号 |
US6977980(B2) |
申请公布日期 |
2005.12.20 |
申请号 |
US20010942198 |
申请日期 |
2001.08.29 |
申请人 |
RAMBUS INC. |
发明人 |
CHANG KUN-YUNG KEN;HUANG CHAOFENG |
分类号 |
H04L7/02;(IPC1-7):H04L7/00 |
主分类号 |
H04L7/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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