发明名称 |
Thick metal layer integrated process flow to improve power delivery and mechanical buffering |
摘要 |
A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
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申请公布号 |
US6977435(B2) |
申请公布日期 |
2005.12.20 |
申请号 |
US20030659044 |
申请日期 |
2003.09.09 |
申请人 |
INTEL CORPORATION |
发明人 |
KIM SARAH E.;MARTELL BOB;AYERS DAVE;LIST R. SCOTT;MOON PETER;GEORGE, LEGAL REPRESENTATIVE ANNA M. |
分类号 |
H01L21/60;H01L21/768;H01L23/36;H01L23/485;H01L23/498;H01L23/528;H01L23/532;(IPC1-7):H01L29/40 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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