| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock control circuit capable of precisely controlling phase relations at high speed, when a multiphase external clock signal is inputted, and frequency dividers are operated with that multiphase input clock signal. <P>SOLUTION: By dealing divided signals formed by frequency division from a multiphase clock signal (CLK11-CLK14) inputted externally, as data and clocks for downstream D flip-flops, time delay of each D flip-flop is canceled, and only the set up time of each D flip-flop becomes an element to determine the frequency of each clock. Clock control of a higher frequency can be performed, by causing this set up time to have a margin further by the use of delay buffers (111-115). <P>COPYRIGHT: (C)2006,JPO&NCIPI |
