| 摘要 |
PROBLEM TO BE SOLVED: To provide a system LSI capable of effectively accessing an external memory when a bus is set to be hierarchical. SOLUTION: Cache memories 120 and 121 are arranged on bus bridges 107 and 108, respectively. A CPU 101 controls a memory field accessed by a scanner interface 114, a CCD compensating section 113, an output image processing section 112, and printer interface 111, and performs coherency control disabling contents of cache memories 120 and 121 if necessary. COPYRIGHT: (C)2006,JPO&NCIPI
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