发明名称 Information processing apparatus with a cache memory and information processing method
摘要 A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main memory to the secondary texture cache in accordance with cache misses of the plurality of texture units, so as to suppress occurrence of thrashing in the secondary texture cache. The cache controlling CPU suppresses occurrence of the refill operation when the plurality of operating units access an identical memory address with a predetermined time difference.
申请公布号 US2005275658(A1) 申请公布日期 2005.12.15
申请号 US20050141700 申请日期 2005.05.31
申请人 SASAKI NOBUO;YAMAZAKI TAKESHI;KUNIMATSU ATSUSHI;YASUKAWA HIDEKI 发明人 SASAKI NOBUO;YAMAZAKI TAKESHI;KUNIMATSU ATSUSHI;YASUKAWA HIDEKI
分类号 G06F12/08;(IPC1-7):G06F12/00;G09G5/36 主分类号 G06F12/08
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