发明名称 ARITHMETIC CIRCUIT, LOGICAL CIRCUIT, READ-ONLY MEMORY, REGISTER, AND SEMICONDUCTOR CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide an arithmetic circuit to be used for an encryption circuit, and a logical circuit, a read-only memory, a register, and a semiconductor circuit including a plurality of logics, in which confidential data can be prevented from being intercepted by electronic analysis by using simple constitution. <P>SOLUTION: Positive/negative logic mixing data buses 102, 108 included in a multiplication circuit 100 transmit n (n&ge;2) bit data in which positive logic and negative logic for bit logic are mixed. An addition part 1000 receives data transmitted from the positive/negative logic mixing data buses 102, 108 and performs addition suited to the logic of the positive/negative logic mixing data buses 102, 108. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005346373(A) 申请公布日期 2005.12.15
申请号 JP20040164761 申请日期 2004.06.02
申请人 RENESAS TECHNOLOGY CORP 发明人 MIYAUCHI SHIGENORI;YAMAGUCHI ATSUO;FUKUSHIMA KAZUHIKO;ASAMI KAZUO
分类号 G06F7/48;G06F7/72;G09C1/00;H04L9/10 主分类号 G06F7/48
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