发明名称 Multi-valued digital information retaining elements and memory devices
摘要 The invention discloses models and methods to create stable binary and non-binary sequential devices comprised of one or more logic functions of which an output signal is uniquely related to an input signal. Methods and apparatus for non-binary single independent input information retaining devices from two logic functions are disclosed. Memory elements using the information retaining devices and methods are also disclosed. Methods and apparatus for n-valued memory devices including n-valued inverters with feedback are disclosed. Binary and non-binary information retaining elements with two logic functions and two independent inputs are disclosed. Also disclosed are n-valued gating devices that can be combined with n-valued information retaining devices to form n-valued memory devices. Methods and apparatus for single non-binary n-valued logic function latches are disclosed. Single non-binary n-valued function methods realizing (n-1)-valued latching methods controlled by an nth state are also disclosed. Two non-binary n-valued logic functions based memory devices retaining the value of a first input and controlled by a second input are disclosed. Ternary, 4-valued and n-valued true latches are disclosed.
申请公布号 US2005278661(A1) 申请公布日期 2005.12.15
申请号 US20050139835 申请日期 2005.05.27
申请人 LABLANS PETER 发明人 LABLANS PETER
分类号 G06F7/49;G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F7/49
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