发明名称 |
INFORMATION PROCESSOR AND INFORMATION PROCESSING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To provide a technology for speeding up data reading by reducing cache mistake. SOLUTION: A two-dimensional texture cache 400 is commonly used from a plurality of texture units 620 to 6n0, and a portion of the texture data of a main memory 10 is stored. A cache control CPU 200 controls a refill operation from the main memory 10 to the two-dimensional texture cache 400 according to the cache mistakes of the plurality of texture units 60 to 6n0 in order to suppress the generation of thrashing in the two-dimensional texture cache 400. The cache control CPU 200 suppress the generation of the refill operation when the plurality of texture units 620 to 6n0 perform access to the same memory address with a predetermined time difference. COPYRIGHT: (C)2006,JPO&NCIPI
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申请公布号 |
JP2005346215(A) |
申请公布日期 |
2005.12.15 |
申请号 |
JP20040162636 |
申请日期 |
2004.05.31 |
申请人 |
SONY COMPUTER ENTERTAINMENT INC;TOSHIBA CORP |
发明人 |
SASAKI NOBUO;YAMAZAKI TAKESHI;KUNIMATSU ATSUSHI;YASUKAWA HIDEKI |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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主权项 |
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地址 |
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