| 摘要 |
A scheme for PLL-based at-speed scan testing in which a clock generation circuit is used to generate different clock signals to scannable flip-flops of an integrated circuit. When the integrated circuit is under at-speed scan test mode of operation, the clock generation circuit receives a scan-clock signal to scan in a test vector to the scannable flip-flops during an input shift phase when shifting is enabled and to scan out a resultant vector from the scannable flip-flops during an output shift phase when shifting is also enabled. However, when shifting is not enabled during a capture phase between the two shift phases, the scan-clock signal triggers a 2-pulse circuit to release two pulses during the capture phase of at-speed scan testing. The two pulses from the 2-pulse circuit are based on an internal PLL-based clock signal. The clock generation circuit may be utilized in single or multiple clock domain systems. In a multiple clock domain environment, separate scan-clock signals may be sent to individual clock domains within an integrated circuit and only the domain to be acted on by a test vector has its respective scan-clock pulsed during the capture phase.
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