System and method to reduce noise in a substrate

摘要

Disclosed herein is a system adapted to reduce noise in a substrate of a chip. The chip may include a substrate having a first well disposed there atop. The first well may be a deep well. A second well and a third may also be disposed within the first well. A first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor. A second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor. A body of the first transistor may be resistively coupled to the second well.