| 摘要 |
Disclosed herein is a method of manufacturing a cell transistor which can achieve an improvement in a short-channel effect of a cell transistor as well as an improvement in a refresh characteristic of the transistor, and can also prevent a reduction in the threshold voltage of the transistor, in relation to DRAM memory cells with high integration. The method comprises the steps of forming a device isolation region, which defines a device separating region, on a silicon substrate, forming a barrier layer on the substrate formed with device isolation region, forming a hard mask, which defines a gate forming region, on the substrate formed with the barrier layer, forming a silicon epitaxial layer on a surface of the substrate through selective epitaxial growth of silicon constituting the surface of the substrate, formed with the hard mask and the barrier layer, and removing the hard mask.
|
