发明名称 METHODS FOR FORMING SEMICONDUCTOR STRUCTURES
摘要 The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.
申请公布号 US2005277249(A1) 申请公布日期 2005.12.15
申请号 US20040855429 申请日期 2004.05.26
申请人 JUENGLING WERNER 发明人 JUENGLING WERNER
分类号 H01L21/00;H01L21/336;H01L21/8242;H01L27/108;H01L29/786;(IPC1-7):H01L21/336 主分类号 H01L21/00
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