| 摘要 |
<p>An orthogonal code generation apparatus can generate a sequence of orthogonal codes without having to prestore orthogonal code sequences in a memory, by applying logic operation on a sequence number and a location number using AND circuits A0, A1, A2, A3, ..., An and an adder circuit (40). A scrambling code generation apparatus computes only the values of registers (12, 14) involved with a feedback operation and a spreading operation, and loads respective values into the registers (12, 14) while shifting the shift register. When all the registers (11-14) store valid values, scrambling codes are generated by a shift operation of the shift register. <IMAGE></p> |
