发明名称 Processing packets based on deadline intervals
摘要 A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.
申请公布号 US6975629(B2) 申请公布日期 2005.12.13
申请号 US20010785768 申请日期 2001.02.16
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 WELIN ANDREW M.
分类号 G10L11/02;H04L12/56;H04L12/64;H04L29/02;H04L29/06;H04M3/00;(IPC1-7):H04L12/28 主分类号 G10L11/02
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