Circuit for correction of differential signal path delays in a PLL

摘要

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) select one of a plurality of input signals and (ii) generate (a) an output signal having a frequency and (b) one or more control signals in response to a skew signal. The second circuit may be configured to generate the skew signal in response to the one or more control signals. The first circuit may be configured to minimize skew between the selected input signal and a feedback of the output signal, in response to the skew signal.