发明名称 Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
摘要 A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from ports in segments and each segment is assigned to one of the program threads. Ordering of segments within packets, and between packets from the same port, is maintained by a scheduler program thread. The scheduler program thread blocks a new assignment of the previously assigned port to a program thread until the program thread to which the port was previously assigned has indicated that it has completed the processing of the segment from that port.
申请公布号 US6976095(B1) 申请公布日期 2005.12.13
申请号 US19990476303 申请日期 1999.12.30
申请人 INTEL CORPORATION 发明人 WOLRICH GILBERT;BERNSTEIN DEBRA;ADILETTA MATTHEW J.
分类号 G06F9/48;G06F15/16;H04L12/56;(IPC1-7):G06F15/16 主分类号 G06F9/48
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