发明名称 |
Negative differential resistance pull up element for DRAM |
摘要 |
A memory cell includes a pull-up element that exhibits a refresh behavior that is dependent on the data value stored in the memory cell. The pull-up element is an NDR FET connected between a high voltage source and a storage node of the memory cell. The NDR FET receives a pulsed gate bias signal, wherein each pulse turns on the NDR FET when a logic HIGH value is stored at the storage node, and further wherein each pulse does not turn on the NDR FET when a logic LOW value is stored at the storage node. In this fashion a DRAM cell (and device) can be operated without a separate refresh cycle.
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申请公布号 |
US2005269628(A1) |
申请公布日期 |
2005.12.08 |
申请号 |
US20050198955 |
申请日期 |
2005.08.08 |
申请人 |
PROGRESSANT TECHNOLOGIES, INC. |
发明人 |
KING TSU-JAE |
分类号 |
G11C11/405;G11C11/406;H01L21/8242;H01L27/105;H01L27/108;H01L27/11;H01L29/423;H01L29/76;H01L29/788;H01L29/792;(IPC1-7):H01L29/76 |
主分类号 |
G11C11/405 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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