Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics

摘要

The present invention provides a semiconductor structure comprising a semiconductor substrate having source and drain diffusion regions located therein, the source and drain diffusion regions being separated by a device channel; and a gate stack located on top of the device channel, the gate stack comprising a high-k gate dielectric, an insulating interlayer and a fully silicided metal gate conductor, the insulating interlayer located between the high-k gate dielectric and the fully silicided metal gate conductor, wherein the insulating interlayer is capable of stabilizing threshold voltage and flatband voltage of the semiconductor structure to a targeted value.