LOW-VOLTAGE SINGLE-LAYER POLYSILICON EEPROM MEMORY CELL

摘要

The present invention is an electronic memory cell (200) and a method for the cell's fabrication comprising a first transistor (201) configured to be coupled to a bit line. The first transistor (201) has an essentially zero voltage drop when activated and is configured to control an operation of the memory cell (200). A second transistor (203) is configured to operate as a memory transistor and is coupled to the first transistor (201). The second transistor (203) is further configured to be programmable with a voltage about equal to a voltage on the bit line.