发明名称 |
High speed receive equalizer architecture |
摘要 |
Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.
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申请公布号 |
US2005271169(A1) |
申请公布日期 |
2005.12.08 |
申请号 |
US20040880959 |
申请日期 |
2004.06.30 |
申请人 |
MOMTAZ AFSHIN;CARESOSA MARIO;CHUNG DAVID;TONIETTO DAVIDE;YIN GUANGMING;CURRIVAN BRUCE;KOLZE THOMAS;FUJIMORI ICHIRO |
发明人 |
MOMTAZ AFSHIN;CARESOSA MARIO;CHUNG DAVID;TONIETTO DAVIDE;YIN GUANGMING;CURRIVAN BRUCE;KOLZE THOMAS;FUJIMORI ICHIRO |
分类号 |
H03G3/30;H03L7/091;H04L7/02;H04L7/033;H04L25/03;H04L27/08;(IPC1-7):H04L27/08 |
主分类号 |
H03G3/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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