RESYNCHRONIZATION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a resynchronization circuit capable of speeding up data transfer with a sufficient migration margin even when the speed of a clock signal used for outputting data is increased.

SOLUTION: A determination circuit 1100 holds and outputs a signal determined according to the phase difference between a determination signal and a reference clock signal (determination result). A synchronization circuit block 1200 holds a received data signal in synchronization with a strobe signal, and then holds and outputs the received data signal in synchronization with a clock signal having the same frequency as that of the reference clock signal and having a phase determined according to the determination result.

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