发明名称 Match circuit for performing pattern recognition in a performance counter
摘要 A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit comprises logic for activating a match_mm signal when a selected N-bit portion of the data matches an N-bit threshold for all bits selected by an N-bit match mask ("mmask") and logic for activating a match_OR signal when at least one of one or more designated bits of the selected N-bit portion of the data is a logic 1 or if there are no designated bits.
申请公布号 US2005273682(A1) 申请公布日期 2005.12.08
申请号 US20040022023 申请日期 2004.12.23
申请人 ADKISSON RICHARD W 发明人 ADKISSON RICHARD W.
分类号 G01R31/28;G06F7/02;G06F11/34;G06F15/00;G06F15/76;(IPC1-7):G06F15/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址