| 摘要 |
PROBLEM TO BE SOLVED: To provide a frequency dividing circuit wherein processing frequency is high, and the occupied physical region and power consumption are small. SOLUTION: A programmable frequency-dividing circuit with symmetrical output is disclosed. The frequency divider includes a non-symmetrical LFSR-based component, operated in series with a symmetrical divider component. Both the LFSR and the symmetrical divider may be programmed to give flexibility. The frequency divider dynamically adjust the divisor of the LFSR component to overcome limitations in the divide resolution due to the series combination of dividers, giving even and odd divisor values. The divider architecture can also provide higher level functions, including synchronization of multiple divider outputs, dynamic switching of divisor values and generation of multi-phased and spaced outputs. The linear feedback shift register (LFSR) component includes a feedback logic circuit, decomposed into multiple stages, to realize the maximum inter-latch operational waiting time of a single gate delay, regardless of the size of the LFSR. COPYRIGHT: (C)2006,JPO&NCIPI
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