发明名称 ENCRYPTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide an encryption circuit capable of coping with a factor being a new cause to the occurrence of a degeneration fault, and including measures to a fault analysis for suppressing a hardware cost and an increase in encryption processing time. SOLUTION: The encryption circuit adopts a private key encryption system for receiving a plain text and a private key 4A, receiving R partial keys Kn obtained from the private key 4A, and encrypting the plain text by executing round arithmetic operations for R times repetitively for the plain text and includes: registers 4G, 4H for storing values of the plain text after the round arithmetic operations; a fault inspection circuit 1A for discriminating the presence and absence of a degeneration fault on the basis of values of the registers 4H, 4G; and a circuit 1B for invalidating the private key 4A when the result of inspection indicates the presence of the degeneration fault. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005340892(A) 申请公布日期 2005.12.08
申请号 JP20040152852 申请日期 2004.05.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIMIZU KAZUYA;SATO TOMOYA;SHIOMI KENTARO;NEMOTO YUSUKE;TORISAKI TADAYUKI;FUJIWARA MUTSUMI
分类号 H04L9/10;G06K19/073;H04K1/00;H04L9/06;(IPC1-7):H04L9/10 主分类号 H04L9/10
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